In this paper, a novel heterostructure junctionless tunnel field effect transistor with silicon-on-nothing technology (SON HS-JLTFET) is proposed. The proposed device has two advantages over conventional JLTFET. First, one decade of increment in the ON current is achieved and Subthreshold swing is improved by 10%. In this device, InAs is used in the source region of SON HS-JLTFET which has a lower energy band gap than Si to achieve thinner tunneling barrier width. Hence, more electron can tunnel from source to channel. As a result, it provides improvements in drain current and Subthreshold swing. The second advantage is that the ambipolar current reduction due to the use of SON technique. In fact, in this technique, air is considered as the gate dielectric which results in decrement in the electric field in the drain/channel junction. This reduced electric field causes increasing the width of the tunneling barrier which results in lower ambipolar current in the drain/channel junction..

In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated. DWG SP RD-TFET is a Silicon-channel TFET with two isolated metal gates (main gate and auxiliary gate) and a source pocket in the channel close to the source-channel junction to increase the carrier tunneling rate. For further enhancement in the tunneling rate, source doping near the source-channel junction, i. e., underneath the auxiliary gate is heavily doped to create more band bending in energy band diagram. Retrograde doping in the channel along with auxiliary gate over the source region also improve device Subthreshold swing and leakage current. Based on our simulation results, excellent electrical characteristics with ION/IOFF ratio > 109, point Subthreshold swing (SS) of 6 mV/dec and high gm/ID ratio at room temperature shows that this tunneling FET can be a promising device for low power applications.

This work presents a sub-nanowatt voltage reference (VR) achieving a high-power supply ripple rejection (PSRR). It utilizes a self-current biasing circuit to reduce the voltage dependency of the output voltage (VREF) to the power supply variations. For low-power operation, all transistors operate in the Subthreshold region. The design's performance is verified through post-layout and Monte Carlo simulations in a standard 180 nm CMOS process. Results show that the proposed bandgap achieves an output voltage of 0.150 V with a PSRR of -81.5 dB at V­­dd = 1V. Notably, it eliminates the need for an additional startup circuit and consumes only 0.72 nW at T = 27°C with Vdd = 0.5V. The proposed voltage reference exhibits a temperature coefficient (TC) of approximately 18 ppm/°C over a temperature range of -20°C to 130°C while without using a trimming circuit a reasonable (σ VREF /μVREF) = 2.3% is obtained. This design's average line sensitivity (LS) is 0.072%/V (Vdd = 0.5V to 1.8V). However, the PSRR and LS values are temperature-dependent. At the high temperature of 130°C (worst-case), the PSRR and LS degrade to approximately -80.45 dB and 0.084 %/V, respectively.  The output noise at the frequency of 1 KHz is obtained as 167.34 nV/ √ Hz. The proposed VR occupies a small active area of 513.5 μm2.

This paper presents a vertical tunnel field effect transistor (TFET) that incorporates two parallel side wall channels. The channel material utilized in this design is Indium Nitride (InN), which is sandwiched between lateral gates. This configuration allows for the amplification of drive current through extended tunneling area, taking advantage of the benefits offered by the vertical structure. InN is a promising channel material due to its high electron mobility and high electron velocity, which enhances the device performance. The impact of critical design parameters on the device performance is comprehensively assessed. The optimal values of a 2D variation matrix of threshold voltage and on-state current can be determined by considering the variation of gate workfunction and source doping density, which are two crucial design measures. Additionally, a statistical analysis is carried out to evaluate the sensitivity of the device main electrical parameters with respect to the variation of critical design parameters. The findings indicate that the device attains a current of 1 mA when in the on-state, with an on/off current ratio of 1.3×1010. Additionally, it exhibits an average Subthreshold swing of 20 mV/dec, and maximum Subthreshold swing of 4.8 mV/dec, leading to reduced power consumption and enhanced switching speeds.

In this paper the impact of the trap assisted tunneling mechanism on the Subthreshold characteristics of the tunneling field effect transistors is investigated. It is shown that the trap assisted tunneling is the dominant charge transfer mechanism before the band to band tunneling starts. Employing a modified SRH formalism, we show that, at the room temperature and for the Subthreshold voltages, the trap assisted tunneling current always dominates and degrades the switching characteristics of the device which is measured by the Subthreshold swing. This approach is applicable to the double gate and the gate-all-around structures where the traps are located in the source-channel tunneling junction. The trap assisted tunneling strongly depends on the electric field and the temperature. The considered transistors in this research are based on the compound semiconductors of groups three and five of periodic table. The effects of various structural parameters and material systems on the trap assisted tunneling current are studied, too.